Linear amplifier

ABSTRACT

A linear amplifier circuit comprising a first differential amplifier (DA  1 ) having a differential input terminals (I+, I−) for receiving a binary input signal, and a differential output terminals (O+,O−), a second differential amplifier (DA 2 ) having input terminals coupled to the differential input terminals (I+, I−). The amplifier further comprises, a third differential amplifier (DA 3 ) coupled in cascade to the second differential amplifier (DA 2 ) and having its output cross-coupled to the differential output terminals in a feedforward connection, and a capacitor (C) coupled to the third differential amplifier (DA 3 ) for determining an increase of a bandwidth of the linear amplifier, a current flowing through the capacitor (C) being proportional with a derivative of the differential input signal (I+, I−).

The invention relates to a linear amplifier. The invention furtherrelates to a limiting amplifier comprising the linear amplifier.

Linear amplifiers are widely used in relatively high frequencyapplications as receivers and transmitters. When the input signals arebinary signals i.e. having a LOW value and HIGH value situated in arelatively large range e.g. GHz the necessary bandwidth of the amplifieris relatively large. Furthermore, the amplifier need to provide arelatively constant gain with a minimum level of distortion for bothrelatively low level signals and high level signals.

U.S. Pat. No. 6,404,285 describes a differential amplifier used in anintermediate frequency, voltage gain amplifier to produce asubstantially linear, differential output signal for both small andlarge differential input signals. The amplifier comprises a pair oftransistors coupled at their emitters and being biased via anothertransistor having a base coupled to the differential input signal via apair of resistors. It is observed that when the amplifier is directlyimplemented in CMOS technology, the resulting amplifier has asubstantially lower amplification because a transconductance of the CMOStransistors is substantially lower, e.g. over 40 times lower than atransconductance of a bipolar transistor. Hence, an increase of theamplifier gain is necessary. Any increase of the gain of the amplifierdetermines a smaller available bandwidth for an input signal because fora given amplifier a so-called gain-bandwidth product is a relativelyconstant parameter.

It is therefore an object of this invention to provide a linearamplifier implemented in CMOS technology that mitigates theabove-mentioned problems.

The invention is defined by the independent claims. The dependent claimsdefine advantageous embodiments.

The cross-coupled output terminals determine a feed-forward determininga supplementary amplification of the input signal. A suitable chosencapacitor's value determines an increase of the available bandwidth ofthe amplifier. Subsequently, rising and falling edges of a binary inputsignal are not substantially distorted.

In an embodiment of the invention the first differential amplifiercomprises a first transistor pair coupled to a common drain transistorpair via resistors means, a current through the common drain transistorpair improving a linearity of the first differential amplifier. Thesecond differential amplifier comprises a second transistor pair beingsupplied with a substantially equal current as the first differentialamplifier.

The third differential amplifier may comprise a third transistor pairhaving their respective source terminal coupled via the capacitor. Letus consider that the first pair of transistors comprises transistorshaving the same area and that the transistors included in the commondrain transistor pair have a different area. Let us further note theresistor means as R and the current flowing through it as i. Thefollowing relations may be written: $\begin{matrix}\left\{ \begin{matrix}{V_{ID} = {2{iR}}} \\{V_{ID} = {\sqrt{\frac{2i_{1}}{\beta_{1}}} - \sqrt{\frac{2i_{3}}{\beta_{3}}} + {iR}}} \\{V_{ID} = {\sqrt{\frac{2i_{3}}{\beta_{3}}} - \sqrt{\frac{2i_{2}}{\beta_{1}}} + {iR}}} \\{i_{3} = {I_{0} - \left( {i_{1} + i_{2}} \right)}}\end{matrix} \right. & (1)\end{matrix}$In relations (1) β₁ and β₃ are coefficients related to the dimensions ofthe pair of transistor and common drain transistors, respectively. V_(T)is a threshold voltage of the transistors. i₁ and i₂ are the currentsthrough the pair of transistors. V_(iD) is the differential input signaland I_(B) is the bias current for both first transistor pair and secondtransistor pair. i₃ is a current through the common drain transistorpair. i₃ is quadratic with respect to the input differential voltageV_(iD) as in eq. (2). $\begin{matrix}{i_{3} = {\frac{I_{0}}{1 + {2\left( \frac{W_{1}}{W_{3}} \right)}}\left( {1 - \frac{\beta_{1}V_{ID}^{2}}{4I_{0}}} \right)}} & (2)\end{matrix}$The differential output current depends on the differential inputvoltage as shown in equation (3): $\begin{matrix}{i_{OD} = {{i_{1} - i_{2}} = {\beta_{1}{\sqrt{\frac{2I_{0}}{\beta_{3}\left( {1 + {2\frac{W_{1}}{W_{3}}}} \right)}} \cdot V_{ID}}\sqrt{1 - \frac{\beta_{1}V_{ID}^{2}}{4I_{0}}}}}} & (3)\end{matrix}$It is to be mentioned here that the term β₁V_(iD) ² has dimension of acurrent. It is further observed that if I_(B) is chosen such thatβ₁V_(iD) ²<<I_(B) then relation (3) reduces to relation (4).$\begin{matrix}{i_{OD} \approx {\beta_{1}{\sqrt{\frac{2I_{0}}{\beta_{3}\left( {1 + {2\frac{W_{1}}{W_{3}}}} \right)}} \cdot V_{ID}}}} & (4)\end{matrix}$Hence, the current is linearly dependent on the differential inputvoltage. When using the capacitor equation (4) may be re-written as inequation (5). $\begin{matrix}{{i_{OD}(t)} \approx {\beta_{1}{\sqrt{\frac{2I_{0}}{\beta_{3}\left( {1 + {2\frac{W_{1}}{W_{3}}}} \right)}} \cdot \left\lbrack {V_{ID} + {{\tau(C)}\frac{\delta\quad V_{ID}}{\delta\quad t}}} \right\rbrack}}} & (5)\end{matrix}$In relation (5) τ(C) is a time-constant depending on the value of thecapacitor and an output impedance of the second transistor pair. If wedenote this impedance as R2 and the capacitor's value as C then thetime-constant equals R2*C. It is easily seen from relation (5) that thecapacitor improve the amplifier performance when binary signals are usedand the term $\frac{\delta\quad V_{ID}}{\delta\quad t}$has a significant value even when the input signal has a relativelysmall value.

In another embodiment, the linear amplifier is used in limiter amplifiercomprising a chain of linear amplifiers. The limiting amplifier furthercomprises a plurality of limiting amplifiers coupled in cascade andfurther coupled to the chain of linear amplifiers and providing alimited differential signal. Limiter amplifiers are widely used inreceivers and transmitters of frequency modulated signals. They usuallycomprise a high gain amplifier cascaded with a Gilbert cell forproviding binary type of signals. When the input signals are alreadybinary and situated in a relatively high frequency range the linearamplifier may comprise a plurality of linear amplifiers as previouslydescribed.

In another embodiment of the invention the limiter amplifier furthercomprises a feedback differential integrator for adjusting an offsetvoltage of the limiter amplifier. A cut-off frequency of the integratoris chosen substantially lower than the frequency range of the inputsignals in the limiter. The integrator provides a relatively constantoutput signal for adjusting the off-set of the limiter.

In another embodiment of the invention at least one of the limitingamplifiers of the plurality of limiting amplifiers has its inputterminals coupled via a series coupled substantially equal resistors forproviding a common mode signal. The common mode signal is provided to areplica biasing circuit generating a compensation signal biasing thechain of linear amplifiers and the plurality of limiting amplifiers. Thecompensation signal is mainly determined by the common mode signal,which in turn is determined by temperature variations. For example anincrease of the temperature determines a decrease in gain of theamplifier and the compensation signal determines a gain of the limiterto be relatively constant.

The replica biasing circuit may comprise a pair of replica transistorshaving coupled their respective terminals i.e. drain to drain, source tosource and gate to gate, their gates being coupled to the common modesignal, a transconductance amplifier generating the compensation signalwhich is proportional with a difference between a reference signal and avoltage in the drains of the of the pair of replica transistors.

The reference signal may be a band-gap voltage generator. The commonmode signal is measured at the input of one of the limiting amplifier.The transconductance amplifier compares the voltages in the drains ofthe pair of replica transistors with the band-gap voltage and generatingan output current that depends on temperature and technological process.The current is further used to adjust the bias currents in the linearamplifiers and limiting amplifiers.

The above and other features and advantages of the invention will beapparent from the following description of the exemplary embodiments ofthe invention with reference to the accompanying drawings, in which:

FIG. 1 depicts a block representation of a linear amplifier according tothe invention,

FIG. 2 depicts a more detailed representation of a linear amplifieraccording to one embodiment of the invention,

FIG. 3 depicts a block diagram of a limiter amplifier according to theinvention,

FIG. 4 depicts a more detailed representation of the limiter amplifieraccording to the invention,

FIG. 1 depicts a block representation of a linear amplifier according tothe invention. The linear amplifier circuit comprises a firstdifferential amplifier DA1 having a differential input terminals I+, I−for receiving a binary input signal and a differential output terminalsO+, O−. The linear amplifier further comprises a second differentialamplifier DA2 having input terminals coupled to the differential inputterminals I+, I−. The linear amplifier circuit includes a thirddifferential amplifier DA3 coupled in cascade to the second differentialamplifier DA2 and having its output terminals O1+, O1− cross-coupled tothe differential output terminals in a feed-forward connection i.e. O1+coupled to O− and O1− coupled to O+. Signs + and − indicatenon-inverting output and inverting output, respectively. Furthermore, aninverting output generates a signal substantially in antiphase to theinput signal and a non-inverting output generates a signal substantiallyin phase with the input signal.

A capacitor C is coupled to the third differential amplifier DA3 fordetermining an increase of a bandwidth of the linear amplifier, acurrent flowing through the capacitor C being proportional with aderivative of the differential input signal I+, I−.

A CMOS implementation of the linear amplifier is shown in FIG. 2. Thefirst differential amplifier DA1 comprises a first transistor pair M1,M6 coupled to a common drain transistor pair M3, M4 via resistors R. Acurrent through the common drain transistor pair 13 improving alinearity of the first differential amplifier DA1 as results fromrelations 1 to 5. The second differential amplifier DA2 comprises asecond transistor pair M2, M5, which is supplied with a substantiallyequal current as the first differential amplifier DA1. It is observedthat the transistors M1, M6, M2, M5 have substantially the same area andare supplied from a same current source I0. Hence, the current throughthe transistors is substantially equal to each other. The thirddifferential amplifier DA3 comprises a third transistor pair M7, M8having their respective source terminal coupled via the capacitor C. Theinput signal I+, I− is linearly replicated in the drains of transistorsM2 and M5 and consequently, in the sources of transistors M7 and M8. Thecurrent flowing in the capacitor is the derivative of the input voltagecross-injecting current at the output nodes through M7 and M8. Thecurrent I1 is small in comparison with the current I0 and the dimensionsof the transistors M7 and M8 are smaller than the dimensions oftransistors M1 and M6. Choosing adequately the dimensions of thetransistors and the time constant R₂C, the small signal bandwidth of thecircuit almost doubles and in a transient state one may observe smallerrise and fall times. This circuit may be cascaded directly with the nextstage without the need of source followers, undesired in thistechnology.

The first four stages are identical and once the signal has beenamplified to reasonable levels, the next four stages can limit the inputsignal accordingly. The next limiting stages are based on differentialpairs except for the last stage where a replica biasing circuit has beenadded (see FIG. 4).

FIG. 3 depicts a block diagram of a limiter amplifier according to theinvention. It comprises a chain of linear amplifiers LIN1, LIN2, LIN3,LIN4 as shown in FIG. 51, a plurality of limiting amplifiers NLN1, NLN2,NLN3, NLN4 coupled in cascade and further coupled to the chain of linearamplifiers LIN1, LIN2, LIN3, LIN4 and providing a limited differentialsignal OUT+, OUT−. The limiter amplifier further comprises a feedbackdifferential integrator A1, R1, R2, R3, R4, C1, C2 for adjusting anoffset voltage of the limiter amplifier. The gain of each linearamplifier LIN1, LIN2, LIN3, LIN4 is chosen around 4 dB for bringingsmall signals present at the input to a sufficient large signal neededby the next limiting amplifiers. Although the process limits thegain-bandwidth product of one stage, gain distribution boosts the totalgain-bandwidth product of the complete limiter. The main requirementhere is to reduce the group-delay distortion of the gain stages byensuring that peaking at high frequency of the linear blocks is limited.Finally a gain of 52 dB is achieved with a total small signal bandwidthof 10 GHz. The feedback differential integrator A1, R1, R2, R3, R4, C1,C2 amplifies the offset from the output and feeds back a correctionsignal at the input necessary to compensate the offset. Using theresistive divider R3, R4 and the 50Ω input resistors the time constantof the loop is increased. Considering that A is the gain of the limiterand neglecting, in a first instance, its frequency roll-off and if τdenotes the time constant of the integrator and α the attenuation of theresistive divider at the input, then, the closed loop gain of thelimiter is: $\begin{matrix}{\frac{V_{O}}{V_{I}} = \frac{A\left( {1 + {j\quad\omega\quad\tau\quad B}} \right)}{\left( {1 + {{AB}\quad\alpha}} \right) + {j\quad\omega\quad\tau\quad B}}} & (6)\end{matrix}$The low-frequency pole, which may be approximated by Aα/τ depends notonly on the integrator time constant τ but also on the attenuationfactor α Hence, one may integrate an effective time-constantcorresponding to a cut-off frequency of 1 KHz with small integrationcapacitors.

FIG. 4 depicts a more detailed representation of the limiter amplifieraccording to the invention. The limiter amplifier further comprises areplica biasing circuit providing a compensation signal Icomp biasingthe chain of linear amplifiers LIN1, LIN2, LIN3, LIN4 and the pluralityof limiting amplifiers NLN1, NLN2, NLN3, NLN4. The replica biasingcircuit comprises a pair of replica transistors MR1, MR2 having coupledtheir respective terminals i.e. drain to drain, source to source andgate to gate, their gates being coupled to the common mode signal. Atransconductance amplifier A2 generates the compensation signal Icompwhich is proportional with a difference between a reference signal VSWand a voltage in the drains of the of the pair of replica transistorsMR1, MR2.

The replica biasing circuit ensures constant swing with temperature andwith a change with temperature of the currents in the limiter forcompensating the decrease in gain of the stages for higher temperatures.The voltage VSW is a bandgap reference voltage. The replica biasingcircuit is matched well with temperature/process with the last stage ofthe limiter. The common-mode voltage VCM is measured at the input of thelast stage. The transconductance amplifier A2 compares the voltages onthe resistors R50 with the voltage VSW adjusting the current I0 in thetails of the circuit with temperature and process. In one embodiment,the resistance of R50 is 50 ohm.

It is remarked that the scope of protection of the invention is notrestricted to the embodiments described herein. Neither is the scope ofprotection of the invention restricted by the reference numerals in theclaims. The word ‘comprising’ does not exclude other parts than thosementioned in the claims. The word ‘a(n)’ preceding an element does notexclude a plurality of those elements. Means forming part of theinvention may both be implemented in the form of dedicated hardware orin the form of a programmed purpose processor. The invention resides ineach new feature or combination of features.

1. A linear amplifier circuit comprising: a first differential amplifier (DA1) having a differential input terminals (I+, I−) for receiving a binary input signal, and a differential output terminals (O+,O−), a second differential amplifier (DA2) having input terminals coupled to the differential input terminals (I+, I−), a third differential amplifier (DA3) coupled in cascade to the second differential amplifier (DA2) and having its output cross-coupled to the differential output terminals in a feed-forward connection, and a capacitor (C) coupled to the third differential amplifier (DA3) for determining an increase of a bandwidth of the linear amplifier, a current flowing through the capacitor (C) being proportional with a derivative of the differential input signal (I+, I−).
 2. A linear amplifier as claimed in claim 1, wherein the first differential amplifier (DA1) comprises a first transistor pair (M1, M6) coupled to a common drain transistor pair (M3, M4) via resistor means (R), a current through the common drain transistor pair (I3) improving a linearity of the first differential amplifier (DA1).
 3. A linear amplifier as claimed din claim 1, wherein the second differential amplifier (DA2) comprises a second transistor pair (M2, M5) being supplied with a substantially equal current as the first differential amplifier (DA1).
 4. A linear amplifier as claimed in claim 1, wherein the third differential amplifier (DA3) comprises a third transistor pair (M7, M8) having their respective source terminal coupled via the capacitor (C).
 5. A limiter amplifier comprising: a chain of linear amplifier circuits (LIN1, LIN2, LIN3, LIN4) as claimed in claim 1, a plurality of limiting amplifiers (NLN1, NLN2, NLN3, NLN4) coupled in cascade and further coupled to the chain of linear amplifiers (LIN1, LIN2, LIN3, LIN4) and providing a limited differential signal (OUT+, OUT−).
 6. A limiter amplifier as claimed in claim 5 further comprising a feedback differential integrator (A1, R1, R2, R3, R4, C1, C2) for adjusting an offset voltage of the limiter amplifier.
 7. A limiter amplifier as claimed in claim 5 wherein at least one of the limiting amplifiers (NLN4) of the plurality of limiting amplifiers (NLN1, NLN2, NLN3, NLN4) has input terminals coupled via series coupled substantially equal resistors (R0) for providing a common mode signal (VCM).
 8. A limiter amplifier as claimed in claim 7 further comprising a replica biasing circuit providing a compensation signal (Icomp) biasing the chain of linear amplifiers (LIN1, LIN2, LIN3, LIN4) and the plurality of limiting amplifiers (NLN1, NLN2, NLN3, NLN4).
 9. A limiter amplifier as claimed in claim 8, wherein the replica biasing circuit comprises: a pair of replica transistors (MR1, MR2) having coupled their respective terminals i.e. drain to drain, source to source and gate to gate, their gates being coupled to the common mode signal, and a transconductance amplifier (A2) generating the compensation signal (Icomp) which is proportional with a difference between a reference signal (VSW) and a voltage in the drains of the of the pair of replica transistors (MR1, MR2). 